Preface |
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vii | |
Part 1 The Fabrics |
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1 | (66) |
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3 | (32) |
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4 | (2) |
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Issues in Digital Integrated Circuit Design |
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6 | (9) |
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Quality Metrics of a Digital Design |
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15 | (16) |
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Cost of an Integrated Circuit |
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16 | (2) |
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Functionality and Robustness |
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18 | (9) |
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27 | (3) |
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Power and Energy Consumption |
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30 | (1) |
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31 | (1) |
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31 | (4) |
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32 | (1) |
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33 | (2) |
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The Manufacturing Process |
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35 | (32) |
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36 | (1) |
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Manufacturing CMOS Integrated Circuits |
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36 | (11) |
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37 | (1) |
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37 | (4) |
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Some Recurring Process Steps |
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41 | (1) |
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Simplified CMOS Process Flow |
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42 | (5) |
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Design Rules---The Contract between Designer and Process Engineer |
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47 | (4) |
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Packaging Integrated Circuits |
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51 | (10) |
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52 | (1) |
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53 | (6) |
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Thermal Considerations in Packaging |
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59 | (2) |
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Perspective---Trends in Process Technology |
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61 | (3) |
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61 | (2) |
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63 | (1) |
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64 | (1) |
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64 | (3) |
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64 | (3) |
Design Methodology Insert A IC LAYOUT |
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67 | (64) |
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71 | (2) |
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71 | (2) |
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73 | (58) |
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74 | (1) |
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74 | (13) |
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A First Glance at the Diode---The Depletion Region |
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75 | (2) |
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77 | (3) |
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Dynamic, or Transient, Behavior |
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80 | (4) |
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The Actual Diode---Secondary Effects |
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84 | (1) |
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85 | (2) |
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87 | (33) |
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A First Glance at the Device |
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87 | (1) |
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The MOS Transistor under Static Conditions |
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88 | (26) |
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The Actual MOS Transistor---Some Secondary Effects |
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114 | (3) |
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SPICE Models for the MOS Transistor |
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117 | (3) |
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A Word on Process Variations |
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120 | (2) |
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Perspective---Technology Scaling |
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122 | (6) |
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128 | (1) |
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129 | (2) |
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130 | (1) |
Design Methodology Insert B Circuit Simulation |
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131 | (46) |
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134 | (1) |
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135 | (42) |
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136 | (1) |
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136 | (2) |
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Interconnect Parameters---Capacitance, Resistance, and Inductance |
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138 | (12) |
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138 | (6) |
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144 | (4) |
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148 | (2) |
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150 | (20) |
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151 | (1) |
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151 | (1) |
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152 | (4) |
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156 | (3) |
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159 | (11) |
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170 | (4) |
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Distributed rc Lines in SPICE |
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170 | (1) |
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Transmission Line Models in SPICE |
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170 | (1) |
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Perspective: A Look into the Future |
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171 | (3) |
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174 | (1) |
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174 | (3) |
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174 | (3) |
Part 2 A Circuit Perspective |
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177 | (132) |
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179 | (56) |
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180 | (1) |
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The Static CMOS Inverter---An Intuitive Perspective |
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180 | (4) |
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Evaluating the Robustness of the CMOS Inverter: The Static Behavior |
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184 | (9) |
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185 | (3) |
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188 | (3) |
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191 | (2) |
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Performance of CMOS Inverter: The Dynamic Behavior |
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193 | (20) |
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Computing the Capacitances |
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194 | (5) |
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Propagation Delay: First-Order Analysis |
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199 | (4) |
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Propagation Delay from a Design Perspective |
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203 | (10) |
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Power, Energy, and Energy Delay |
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213 | (16) |
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Dynamic Power Consumption |
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214 | (9) |
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223 | (2) |
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225 | (2) |
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Analyzing Power Consumption Using SPICE |
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227 | (2) |
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Perspective: Technology Scaling and its Impact on the Inverter Metrics |
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229 | (3) |
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232 | (1) |
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233 | (2) |
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233 | (2) |
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Designing Combinational Logic Gates in CMOS |
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235 | (74) |
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236 | (1) |
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236 | (48) |
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237 | (26) |
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263 | (6) |
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269 | (15) |
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284 | (19) |
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Dynamic Logic: Basic Principles |
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284 | (3) |
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Speed and Power Dissipation of Dynamic Logic |
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287 | (3) |
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Signal Integrity Issues in Dynamic Design |
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290 | (5) |
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295 | (8) |
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303 | (3) |
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How to Choose a Logic Style? |
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303 | (1) |
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Designing Logic for Reduced Supply Voltages |
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303 | (3) |
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306 | (1) |
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307 | (2) |
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308 | (1) |
Design Methodology Insert C How to Simulate Complex Logic Circuits |
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309 | (10) |
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Representing Digital Data as a Continuous Entity |
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310 | (1) |
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Representing Data as a Discrete Entity |
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310 | (5) |
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Using Higher-Level Data Models |
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315 | (4) |
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317 | (2) |
Design Methodology Insert D Layout Techniques for Complex Gates |
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319 | (56) |
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Designing Sequential Logic Circuits |
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325 | (50) |
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326 | (4) |
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Timing Metrics for Sequential Circuits |
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327 | (1) |
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Classification of Memory Elements |
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328 | (2) |
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Static Latches and Registers |
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330 | (14) |
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The Bistability Principle |
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330 | (2) |
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Multiplexer-Based Latches |
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332 | (1) |
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Master-Slave Edge-Triggered Register |
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333 | (6) |
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Low-Voltage Static Latches |
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339 | (2) |
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Static SR Flip-Flops---Writing Data by Pure Force |
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341 | (3) |
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Dynamic Latches and Registers |
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344 | (10) |
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Dynamic Transmission-Gate Edge-triggered Registers |
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344 | (2) |
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C2MOS---A Clock-Skew Insensitive Approach |
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346 | (4) |
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True Single-Phase Clocked Register (TSPCR) |
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350 | (4) |
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Alternative Register Styles* |
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354 | (4) |
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354 | (2) |
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Sense-Amplifier-Based Registers |
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356 | (2) |
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Pipelining: An Approach to Optimize Sequential Circuits |
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358 | (6) |
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Latch- versus Register-Based Pipelines |
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360 | (1) |
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NORA-CMOS---A Logic Style for Pipelined Structures |
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361 | (3) |
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Nonbistable Sequential Circuits |
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364 | (6) |
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364 | (3) |
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Monostable Sequential Circuits |
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367 | (1) |
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368 | (2) |
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Perspective: Choosing a Clocking Strategy |
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370 | (1) |
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371 | (1) |
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372 | (3) |
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372 | (3) |
Part 3 A System Perspective |
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375 | (52) |
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Implementation Strategies for Digital ICS |
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377 | (50) |
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378 | (4) |
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From Custom to Semicustom and Structured-Array Design Approaches |
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382 | (1) |
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383 | (1) |
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Cell-Based Design Methodology |
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384 | (15) |
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385 | (5) |
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390 | (2) |
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Macrocells, Megacells and Intellectual Property |
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392 | (4) |
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396 | (3) |
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Array-Based Implementation Approaches |
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399 | (21) |
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Prediffused (or Mask-Programmable) Arrays |
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399 | (5) |
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404 | (16) |
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Perspective---The Implementation Platform of the Future |
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420 | (3) |
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423 | (1) |
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423 | (4) |
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424 | (3) |
Design Methodology Insert E Characterizing Logic and Sequential Cells |
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427 | (8) |
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434 | (1) |
Design Methodology Insert F Design Synthesis |
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435 | (118) |
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443 | (2) |
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445 | (46) |
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446 | (1) |
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446 | (14) |
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Capacitance and Reliability---Cross Talk |
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446 | (3) |
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Capacitance and Performance in CMOS |
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449 | (11) |
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460 | (9) |
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Resistance and Reliability---Ohmic Voltage Drop |
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460 | (2) |
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462 | (2) |
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Resistance and Performance---RC Delay |
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464 | (5) |
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469 | (11) |
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Inductance and Reliability---Voltage Drop |
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469 | (6) |
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Inductance and Performance---Transmission-line Effects |
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475 | (5) |
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Advanced Interconnect Techniques |
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480 | (7) |
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480 | (6) |
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Current-Mode Transmission Techniques |
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486 | (1) |
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Perspective: Networks-on-a-Chip |
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487 | (1) |
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488 | (1) |
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489 | (2) |
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489 | (2) |
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Timing Issues in Digital Circuits |
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491 | (62) |
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492 | (1) |
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Timing Classification of Digital Systems |
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492 | (3) |
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492 | (1) |
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Mesochronous interconnect |
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493 | (1) |
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Plesiochronous Interconnect |
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493 | (1) |
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Asynchronous Interconnect |
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494 | (1) |
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Synchronous Design---An In-depth Perspective |
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495 | (24) |
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Synchronous Timing Basics |
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495 | (7) |
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Sources of Skew and Jitter |
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502 | (6) |
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Clock-Distribution Techniques |
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508 | (8) |
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516 | (3) |
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Self-Timed Circuit Design* |
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519 | (15) |
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Self-Timed Logic---An Asynchronous Technique |
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519 | (3) |
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Completion-Signal Generation |
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522 | (4) |
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526 | (5) |
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Practical Examples of Self-Timed Logic |
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531 | (3) |
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Synchronizers and Arbiters* |
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534 | (5) |
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Synchronizers---Concept and Implementation |
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534 | (4) |
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538 | (1) |
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Clock Synthesis and Synchronization Using a Phase-Locked Loop* |
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539 | (7) |
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540 | (2) |
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542 | (4) |
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Future Directions and Perspectives |
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546 | (4) |
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Distributed Clocking Using DLLs |
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546 | (2) |
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Optical Clock Distribution |
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548 | (1) |
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Synchronous versus Asynchronous Design |
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549 | (1) |
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550 | (1) |
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551 | (2) |
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551 | (2) |
Design Methodology Insert G Design Verification |
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553 | (168) |
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557 | (2) |
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Designing Arithmetic Building Blocks |
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559 | (64) |
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560 | (1) |
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Datapaths in Digital Processor Architectures |
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560 | (1) |
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561 | (25) |
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The Binary Adder: Definitions |
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561 | (3) |
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The Full Adder: Circuit Design Considerations |
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564 | (7) |
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The Binary Adder: Logic Design Considerations |
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571 | (15) |
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586 | (8) |
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The Multiplier: Definitions |
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586 | (1) |
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Partial-Product Generation |
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587 | (2) |
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Partial-Product Accumulation |
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589 | (4) |
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593 | (1) |
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594 | (1) |
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594 | (2) |
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595 | (1) |
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596 | (1) |
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Other Arithmetic Operators |
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596 | (4) |
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Power and Speed Trade-offs in Datapath Structures* |
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600 | (18) |
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Design Time Power-Reduction Techniques |
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601 | (10) |
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Run-Time Power Management |
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611 | (6) |
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Reducing the Power in Standby (or Sleep) Mode |
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617 | (1) |
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Perspective: Design as a Trade-off |
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618 | (1) |
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619 | (1) |
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620 | (3) |
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621 | (2) |
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Designing Memory and Array Structures |
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623 | (98) |
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624 | (10) |
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625 | (2) |
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Memory Architectures and Building Blocks |
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627 | (7) |
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634 | (38) |
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634 | (13) |
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Nonvolatile Read-Write Memories |
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647 | (10) |
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Read-Write Memories (RAM) |
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657 | (13) |
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Contents-Addressable or Associative Memory (CAM) |
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670 | (2) |
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Memory Peripheral Circuitry* |
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672 | (21) |
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672 | (7) |
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679 | (7) |
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686 | (3) |
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689 | (1) |
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689 | (4) |
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Memory Reliability and Yield* |
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693 | (8) |
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693 | (5) |
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698 | (3) |
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Power Dissipation in Memories* |
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701 | (6) |
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Sources of Power Dissipation in Memories |
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701 | (1) |
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Partitioning of the Memory |
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702 | (1) |
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Addressing the Active Power Dissipation |
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702 | (2) |
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Data-Retention Dissipation |
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704 | (3) |
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707 | (1) |
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Case Studies in Memory Design |
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707 | (7) |
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The Programmable Logic Array (PLA) |
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707 | (3) |
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710 | (2) |
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A 1-Gbit NAND Flash Memory |
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712 | (2) |
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Perspective: Semiconductor Memory Trends and Evolutions |
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714 | (2) |
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716 | (1) |
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717 | (4) |
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718 | (3) |
Design Methodology Insert H Validation and Test of Manufactured Circuits |
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721 | (18) |
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721 | (1) |
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722 | (1) |
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723 | (11) |
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Issues in Design for Testability |
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723 | (2) |
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725 | (1) |
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726 | (3) |
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729 | (1) |
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Built-in Self-Test (BIST) |
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730 | (4) |
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734 | (3) |
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734 | (2) |
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Automatic Test-Pattern Generation (ATPG) |
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736 | (1) |
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737 | (1) |
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737 | (2) |
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737 | (2) |
Problem Solutions |
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739 | (6) |
Index |
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745 | |