List of Abbreviations |
|
xi | |
Preface |
|
xv | |
CHAPTER 1 ΣΔ ADCs: Principles, Architectures, and State of the Art |
|
1 | (66) |
|
1.1. Analog-to-Digital Conversion: Fundamentals |
|
|
2 | (5) |
|
|
3 | (1) |
|
|
3 | (4) |
|
1.2. Oversampling ΣΔ ADCs: Fundamentals |
|
|
7 | (13) |
|
|
7 | (1) |
|
|
8 | (3) |
|
1.2.3. Basic architecture of oversampling ΣΔ ADCs |
|
|
11 | (4) |
|
1.2.4. Performance metrics |
|
|
15 | (2) |
|
|
17 | (3) |
|
1.3. Single-Loop ΣΔ Architectures |
|
|
20 | (14) |
|
1.3.1. 1st-order ΣΔ modulator |
|
|
20 | (4) |
|
1.3.2. 2nd-order ΣΔ modulator |
|
|
24 | (3) |
|
1.3.3. High-order ΣΔ modulators |
|
|
27 | (16) |
|
|
27 | (1) |
|
|
28 | (3) |
|
|
31 | (2) |
|
Non-linear stabilization techniques |
|
|
33 | (1) |
|
1.4. Cascade ΣΔ Architectures |
|
|
34 | (9) |
|
1.5. Multi-Bit ΣΔ Architectures |
|
|
43 | (9) |
|
|
45 | (1) |
|
1.5.1. Element trimming and analog calibration |
|
|
46 | (1) |
|
1.5.2. Digital correction |
|
|
47 | (1) |
|
1.5.3. Dynamic element matching |
|
|
48 | (1) |
|
|
49 | (3) |
|
Leslie-Singh architecture |
|
|
49 | (1) |
|
|
50 | (1) |
|
|
50 | (2) |
|
1.6. Parallel ΣΔ Architectures |
|
|
52 | (2) |
|
1.6.1. Frequency division multiplexing |
|
|
53 | (1) |
|
1.6.2. Time division multiplexing |
|
|
53 | (1) |
|
1.6.3. Code division multiplexing |
|
|
54 | (1) |
|
1.7. State of the Art in ΣΔ ADCs |
|
|
54 | (11) |
|
|
65 | (2) |
CHAPTER 2 Non-Ideal Performance of ΣΔ Modulators |
|
67 | (74) |
|
|
68 | (9) |
|
|
68 | (1) |
|
2.1.1. Single-loop ΣΔ modulators |
|
|
69 | (3) |
|
|
69 | (1) |
|
|
70 | (1) |
|
|
71 | (1) |
|
2.1.2. Cascade ΣΔ modulators |
|
|
72 | (5) |
|
|
77 | (6) |
|
2.2.1. Single-loop EA modulators |
|
|
77 | (2) |
|
|
77 | (1) |
|
|
78 | (1) |
|
2.2.2. Cascade EA modulators |
|
|
79 | (4) |
|
2.3. Integrator Settling Error |
|
|
83 | (25) |
|
2.3.1. Model for the transient response of SC integrators |
|
|
84 | (8) |
|
|
84 | (1) |
|
Transient during integration |
|
|
85 | (3) |
|
Transient during sampling |
|
|
88 | (3) |
|
Integration-sampling process |
|
|
91 | (1) |
|
2.3.2. Validation of the proposed model |
|
|
92 | (3) |
|
Comparison with experimental results |
|
|
92 | (1) |
|
Comparison with traditional models |
|
|
93 | (2) |
|
2.3.3. Effect of the amplifier finite gain-bandwidth product |
|
|
95 | (4) |
|
Single-loop ΣΔ modulators |
|
|
97 | (1) |
|
|
97 | (2) |
|
2.3.4. Effect of the amplifier finite slew rate |
|
|
99 | (3) |
|
2.3.5. Effect of the switch finite on-resistance |
|
|
102 | (6) |
|
Effect on an ideal integrator |
|
|
102 | (1) |
|
Effect on the amplifier GB |
|
|
103 | (2) |
|
Effect on the amplifier SR |
|
|
105 | (3) |
|
|
108 | (16) |
|
2.4.1. Noise in track-and-holds |
|
|
109 | (4) |
|
|
110 | (1) |
|
Sampled-and-held component |
|
|
110 | (1) |
|
|
111 | (2) |
|
2.4.2. Noise in SC integrators |
|
|
113 | (9) |
|
Switches controlled by ø1 |
|
|
114 | (1) |
|
Switches controlled by ø2 |
|
|
115 | (1) |
|
|
116 | (3) |
|
|
119 | (1) |
|
|
120 | (2) |
|
2.4.3. Circuit noise in ΣΔ modulators |
|
|
122 | (3) |
|
Fully-differential circuitry |
|
|
123 | (1) |
|
|
124 | (1) |
|
2.6. Sources of Distortion |
|
|
125 | (14) |
|
2.6.1. Distortion due to the non-linear capacitors |
|
|
126 | (4) |
|
2.6.2. Distortion due to the amplifier non-linear gain |
|
|
130 | (3) |
|
2.6.3. Distortion due to the switch non-linear on-resistance |
|
|
133 | (5) |
|
2.6.4. Distortion due to the non-linear settling |
|
|
138 | (1) |
|
|
139 | (2) |
CHAPTER 3 A Wideband ΣΔ Modulator in 3.3-V 0.35-μm CMOS |
|
141 | (52) |
|
|
142 | (1) |
|
|
143 | (8) |
|
3.3. Switched-Capacitor Implementation |
|
|
151 | (2) |
|
3.4. Specifications for the Building Blocks |
|
|
153 | (7) |
|
|
153 | (6) |
|
|
153 | (4) |
|
Fine-tuning of blocks specs |
|
|
157 | (2) |
|
3.4.2. Integrator scaling |
|
|
159 | (1) |
|
3.5. Design of the Building Blocks |
|
|
160 | (17) |
|
|
160 | (8) |
|
|
162 | (4) |
|
|
166 | (2) |
|
|
168 | (1) |
|
|
169 | (1) |
|
|
170 | (3) |
|
3.5.5. Programmable A/D/A converter |
|
|
173 | (3) |
|
|
173 | (1) |
|
|
174 | (1) |
|
|
175 | (1) |
|
3.5.6. Clock phase generator |
|
|
176 | (1) |
|
3.6. Layout and Prototyping |
|
|
177 | (2) |
|
3.7. Experimental Results |
|
|
179 | (9) |
|
3.7.1. Performance of the A/D/A converter |
|
|
182 | (1) |
|
3.7.2. Influence of jitter noise |
|
|
182 | (1) |
|
3.7.3. Influence of settling errors |
|
|
183 | (2) |
|
3.7.4. Influence of switching noise |
|
|
185 | (3) |
|
|
188 | (1) |
|
3.9. Performance Comparison with the State of the Art |
|
|
189 | (3) |
|
|
192 | (1) |
CHAPTER 4 AΣΔ Modulator in 2.5-V 0.25-μm CMOS for ADSL/ADSL+ |
|
193 | (36) |
|
|
195 | (3) |
|
4.2. Switched-Capacitor Implementation |
|
|
198 | (1) |
|
4.3. Specifications for the Building Blocks |
|
|
198 | (7) |
|
4.4. Design of the Building Blocks |
|
|
205 | (12) |
|
|
205 | (4) |
|
|
205 | (2) |
|
|
207 | (1) |
|
|
207 | (2) |
|
|
209 | (1) |
|
|
210 | (2) |
|
|
212 | (1) |
|
|
212 | (2) |
|
|
212 | (2) |
|
|
214 | (1) |
|
4.4.6. Clock phase generator |
|
|
214 | (1) |
|
|
215 | (18) |
|
Reference voltage generator |
|
|
215 | (2) |
|
|
217 | (1) |
|
|
217 | (1) |
|
4.5. Layout and Prototyping |
|
|
217 | (2) |
|
4.6. Experimental Results |
|
|
219 | (4) |
|
|
223 | (2) |
|
4.8. Performance Comparison with the State of the Art |
|
|
225 | (3) |
|
|
228 | (1) |
CHAPTER 5 A ΣΔ Modulator with Programmable Signal Gain for Automotive Sensor Interfaces |
|
229 | (30) |
|
5.1. Basic Design Considerations |
|
|
231 | (2) |
|
5.2. Architecture Selection and High-Level Sizing |
|
|
233 | (6) |
|
5.2.1. Modulator architecture |
|
|
235 | (1) |
|
|
235 | (4) |
|
5.2.3. High-level sizing and building-block specifications |
|
|
239 | (1) |
|
5.3. Design of the Building Blocks |
|
|
239 | (10) |
|
|
239 | (4) |
|
|
243 | (1) |
|
|
244 | (2) |
|
|
246 | (1) |
|
|
246 | (3) |
|
5.4. Layout and Prototyping |
|
|
249 | (2) |
|
5.5. Experimental Results |
|
|
251 | (5) |
|
|
256 | (3) |
APPENDIX A An Expandible Family of Cascade ΣΔ Modulators |
|
259 | (8) |
|
A.1. Topology Description |
|
|
259 | (4) |
|
A.2. Non-Ideal Performance |
|
|
263 | (4) |
APPENDIX B Power Estimator for Cascade ΣΔ Modulators |
|
267 | (8) |
|
B.1. Dominant Error Mechanisms |
|
|
267 | (2) |
|
B.2. Estimation of Power Consumption |
|
|
269 | (6) |
REFERENCES |
|
275 | (18) |
Index |
|
293 | |