Cmos Cascade Sigma-delta Modulators for Sensors and Telecom

by ; ; ; ;
Format: Hardcover
Pub. Date: 2006-09-30
Publisher(s): Springer Verlag
List Price: $219.99

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Summary

CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. Main focus is on cascade architectures, although considerations pertaining to circuits and error analysis are general and hence valid for other architectures. The book differs from others in the complete, in-depth coverage of SC circuit errors, in the detailed elaboration and description of practical design plan, and in the thorough presentation of considerations leading to practical high-performance designs. Another differentiating feature of this book is the coverage into a unified description of largely different application areas. On the one hand, sensor front-ends, where the limiting factor is thermal noise. On the other, wire-line telecom front-ends, where the limiting factor is linked to the dynamic behavior of the building blocks. The book starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. This presentation is both complete and comprehensive. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allow the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors. CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators. In this sense, the book is intended for a large audience: from mixed-signal designers who want to optimize and to shorten the design cycle of sigma-delta modulators with challenging specifications, to non-experienced readers who want a comprehensive and practical description of sigma-delta design and SC errors.

Table of Contents

List of Abbreviations xi
Preface xv
CHAPTER 1 ΣΔ ADCs: Principles, Architectures, and State of the Art 1(66)
1.1. Analog-to-Digital Conversion: Fundamentals
2(5)
1.1.1. Sampling
3(1)
1.1.2. Quantization
3(4)
1.2. Oversampling ΣΔ ADCs: Fundamentals
7(13)
1.2.1. Oversampling
7(1)
1.2.2. Noise-shaping
8(3)
1.2.3. Basic architecture of oversampling ΣΔ ADCs
11(4)
1.2.4. Performance metrics
15(2)
1.2.5. Ideal performance
17(3)
1.3. Single-Loop ΣΔ Architectures
20(14)
1.3.1. 1st-order ΣΔ modulator
20(4)
1.3.2. 2nd-order ΣΔ modulator
24(3)
1.3.3. High-order ΣΔ modulators
27(16)
Stability concerns
27(1)
Optimized NTFs
28(3)
High-order topologies
31(2)
Non-linear stabilization techniques
33(1)
1.4. Cascade ΣΔ Architectures
34(9)
1.5. Multi-Bit ΣΔ Architectures
43(9)
Influence of DAC errors
45(1)
1.5.1. Element trimming and analog calibration
46(1)
1.5.2. Digital correction
47(1)
1.5.3. Dynamic element matching
48(1)
1.5.4. Dual-quantization
49(3)
Leslie-Singh architecture
49(1)
Single-loop ΣΔMus
50(1)
Cascade ΣΔMus
50(2)
1.6. Parallel ΣΔ Architectures
52(2)
1.6.1. Frequency division multiplexing
53(1)
1.6.2. Time division multiplexing
53(1)
1.6.3. Code division multiplexing
54(1)
1.7. State of the Art in ΣΔ ADCs
54(11)
1.8. Summary
65(2)
CHAPTER 2 Non-Ideal Performance of ΣΔ Modulators 67(74)
2.1. Integrator Leakage
68(9)
Leaky integrator
68(1)
2.1.1. Single-loop ΣΔ modulators
69(3)
1st-order loop
69(1)
2nd-order loop
70(1)
Lth-order loops
71(1)
2.1.2. Cascade ΣΔ modulators
72(5)
2.2. Capacitor Mismatch
77(6)
2.2.1. Single-loop EA modulators
77(2)
2nd-order loop
77(1)
Lth-order loops
78(1)
2.2.2. Cascade EA modulators
79(4)
2.3. Integrator Settling Error
83(25)
2.3.1. Model for the transient response of SC integrators
84(8)
SC integrator model
84(1)
Transient during integration
85(3)
Transient during sampling
88(3)
Integration-sampling process
91(1)
2.3.2. Validation of the proposed model
92(3)
Comparison with experimental results
92(1)
Comparison with traditional models
93(2)
2.3.3. Effect of the amplifier finite gain-bandwidth product
95(4)
Single-loop ΣΔ modulators
97(1)
Cascade ΣΔ modulators
97(2)
2.3.4. Effect of the amplifier finite slew rate
99(3)
2.3.5. Effect of the switch finite on-resistance
102(6)
Effect on an ideal integrator
102(1)
Effect on the amplifier GB
103(2)
Effect on the amplifier SR
105(3)
2.4. Circuit Noise
108(16)
2.4.1. Noise in track-and-holds
109(4)
Track component
110(1)
Sampled-and-held component
110(1)
Folding-back effect
111(2)
2.4.2. Noise in SC integrators
113(9)
Switches controlled by ø1
114(1)
Switches controlled by ø2
115(1)
Opamp noise
116(3)
Noise in the references
119(1)
Total noise
120(2)
2.4.3. Circuit noise in ΣΔ modulators
122(3)
Fully-differential circuitry
123(1)
2.5. Clock Jitter
124(1)
2.6. Sources of Distortion
125(14)
2.6.1. Distortion due to the non-linear capacitors
126(4)
2.6.2. Distortion due to the amplifier non-linear gain
130(3)
2.6.3. Distortion due to the switch non-linear on-resistance
133(5)
2.6.4. Distortion due to the non-linear settling
138(1)
2.7. Summary
139(2)
CHAPTER 3 A Wideband ΣΔ Modulator in 3.3-V 0.35-μm CMOS 141(52)
3.1. Design Methodology
142(1)
3.2. Topology Selection
143(8)
3.3. Switched-Capacitor Implementation
151(2)
3.4. Specifications for the Building Blocks
153(7)
3.4.1. Modulator sizing
153(6)
Fast modulator sizing
153(4)
Fine-tuning of blocks specs
157(2)
3.4.2. Integrator scaling
159(1)
3.5. Design of the Building Blocks
160(17)
3.5.1. Amplifiers
160(8)
Front-end amplifier
162(4)
Remaining amplifiers
166(2)
3.5.2. Comparators
168(1)
3.5.3. Switches
169(1)
3.5.4. Capacitors
170(3)
3.5.5. Programmable A/D/A converter
173(3)
ND converter
173(1)
D/A converter
174(1)
Control circuitry
175(1)
3.5.6. Clock phase generator
176(1)
3.6. Layout and Prototyping
177(2)
3.7. Experimental Results
179(9)
3.7.1. Performance of the A/D/A converter
182(1)
3.7.2. Influence of jitter noise
182(1)
3.7.3. Influence of settling errors
183(2)
3.7.4. Influence of switching noise
185(3)
3.8. Performance Summary
188(1)
3.9. Performance Comparison with the State of the Art
189(3)
3.10. Summary
192(1)
CHAPTER 4 AΣΔ Modulator in 2.5-V 0.25-μm CMOS for ADSL/ADSL+ 193(36)
4.1. Topology Selection
195(3)
4.2. Switched-Capacitor Implementation
198(1)
4.3. Specifications for the Building Blocks
198(7)
4.4. Design of the Building Blocks
205(12)
4.4.1. Amplifiers
205(4)
Front-end amplifiers
205(2)
Back-end amplifiers
207(1)
Non-linearities
207(2)
4.4.2. Comparators
209(1)
4.4.3. Switches
210(2)
4.4.4. Capacitors
212(1)
4.4.5. A/D/A converter
212(2)
A/D converter
212(2)
D/A converter
214(1)
4.4.6. Clock phase generator
214(1)
4.4.7. Auxiliary blocks
215(18)
Reference voltage generator
215(2)
Master current generator
217(1)
Anti-aliasing filter
217(1)
4.5. Layout and Prototyping
217(2)
4.6. Experimental Results
219(4)
4.7. Performance Summary
223(2)
4.8. Performance Comparison with the State of the Art
225(3)
4.9. Summary
228(1)
CHAPTER 5 A ΣΔ Modulator with Programmable Signal Gain for Automotive Sensor Interfaces 229(30)
5.1. Basic Design Considerations
231(2)
5.2. Architecture Selection and High-Level Sizing
233(6)
5.2.1. Modulator architecture
235(1)
5.2.2. SC implementation
235(4)
5.2.3. High-level sizing and building-block specifications
239(1)
5.3. Design of the Building Blocks
239(10)
5.3.1. Amplifiers
239(4)
5.3.2. Comparators
243(1)
5.3.3. Switches
244(2)
5.3.4. Capacitor arrays
246(1)
5.3.5. Auxiliary blocks
246(3)
5.4. Layout and Prototyping
249(2)
5.5. Experimental Results
251(5)
5.6. Summary
256(3)
APPENDIX A An Expandible Family of Cascade ΣΔ Modulators 259(8)
A.1. Topology Description
259(4)
A.2. Non-Ideal Performance
263(4)
APPENDIX B Power Estimator for Cascade ΣΔ Modulators 267(8)
B.1. Dominant Error Mechanisms
267(2)
B.2. Estimation of Power Consumption
269(6)
REFERENCES 275(18)
Index 293

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